1. Field of the Invention
The present invention relates generally to the field of semiconductor device manufacturing, and more particularly to electro static discharge (ESD) protection. With still greater particularity the present invention relates to an improved interconnection structures and methods for connecting a separate electro static discharge (ESD) protection circuit to another circuit not on the same die.
2. Description of the Background Art
Protection of a semiconductor integrated circuit (IC) from harmful effects of ESD is conventionally provided in form of special ESD protection circuits and devices located near input/output (I/O) pads on an IC chip, sometimes also referred to as a die. Off-chip ESD protection methods wherein the protection circuit or device is in the same package but not on the same IC chip, are also known in the art. Off-chip techniques are attractive as they reserve the valuable layout area of a high-performance IC chip for its primary circuit function. One such technique, illustrated in FIG. 1A and described by Segaram, Fjelstad, et al. (U.S. Pat. No. 6,933,610), uses wire bonds 10 to connect an external connection lead 11 on a chip carrier or substrate 12 first to an ESD protection device 13, which is mounted on an intermediate substrate 14, and then to an I/O contact 16 of an IC chip 17 that has no on-chip ESD protection. In a variation of the technique, the ESD protection device 13 and substrate 14 of FIG. 1A are replaced as shown in FIG. 1B by an ESD protection chip 15 that includes an ESD protection circuit. While this and other known techniques may be effective under some conditions, they have certain shortcomings that can limit IC performance, especially as technology advances to smaller feature size and faster operating speed. An ideal ESD protection circuit should act as a lightning arrester that is invisible in normal operation but shorts a high voltage surge to ground, bypassing all circuit elements and devices on the IC. A wire bond in series with an I/O connection to a chip, as shown in FIGS. 1A and 1B, has inductance that will not be invisible at high frequency, and thus will be a serious limitation with increasing operating speed of digital and analog ICs. A wire bond connected in parallel with a lower inductance I/O connection of the chip to an external lead, may be invisible at high operating speed, but the series inductance of the wire bond in this case prevents the off-chip ESD protection circuit from acting quickly as a good short circuit, and thus the initial magnitude of an ESD stress voltage on the I/O contact of the IC chip may be excessive, especially for smaller semiconductor feature size and operating voltage on the chip.
An off-chip ESD protection circuit connected with lower inductance and lower impedance, is therefore desirable, especially to keep pace with improvements in IC technology.